基于FPGA的在线可重配置数字下变频器的设计与实现

研究基于现场可编程门阵列(FPGA)的在线可重配置数字下变频器,实现了根据输入信号的3个参数(中频信号频率、中频信号带宽和中频信号采样率)自动生成最优的数字下变频器(DDC)结构和DDC参数的方法. 同时实现了一种优化的FIR滤波器,与传统FIR滤波器相比,利用FIR滤波器线性相位和系数对称的性质,采用预相加的方法减少1/2的乘法运算量,实现了资源占用率和速度之间的平衡,节省FPGA资源. 实验结果表明了该方法的灵活性和有效性. 

Design and Implementation of the On-Line Configurable Digital Down Converter (DDC) Based on FPGA

An on-line reconfigurable DDC of FPGA is designed and implemented in this research. It could produce automatically the optimal DDC structure and DDC parameters by utilizing 3 parameters of the input signal (the frequency, the bandwidth and the sampling rate of IF signal). A new kind of optimal finite impulse response(FIR) filter was designed. Employing the property of linear phase and coefficient symmetry and using pre-add method, the optimal FIR filter could reduce half as the amount of the multiplication computation as the traditional FIR filter. Therefore, the balance between the resource occupation ratio and speed could be realized and it helps saving the FPGA resources. Experimental results show the flexibility and effectiveness of the presented method.