面向同步时序电路的电路并行测试生成算法

面对VLSI设计规模日益增大的挑战，除了电路并行以外，其它已有的基本并行策略都无法从根本上解决测试生成的复杂性问题，然而，已有的电路并行测试生成算法并未取得理想的结果，尤其对时序电路，因此，如何划分电路，成为电路并行算法的设计基础和成功的关键，面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。对Benchmark-89电路的实验结果表明，基于G-F二值算法和BWFSF算法的电路并行测试生成算法在有效减少存储空间消耗的同时，还能够获得稳定的加速比。

Novel Circuit-parallel Test Generation Algorithm for Synchronous Sequential Circuit

Facing the challenge of design scale of VLSI becoming larger,except for circuit parallel,the existing basic parallel approaches cannot solve test generation complexity problems radically.However,the existing circuit parallel test generation algorithms fail get good results,especially for sequential circuit.Therefore,how to partition circuit becomes a key to the design base and success.BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with flip-flop as core.The experimental results on ISCAS89 reveal that,based on G-F two values and BWFSF algorithm,the circuit parallel test generation algorithm GFFCP is able to effectively decrease memory overhead while getting steady speedup.