低密度奇偶检验码译码的高效量化算法

为降低低密度奇偶检验码译码的硬件实现复杂度,提出了一种可变步长均匀量化"和积"译码算法。该算法分为两步进行:首先,检验节点和变量节点的外信息都以相同的量化步长进行均匀量化而进行迭代译码;然后,当迭代达到预定的次数时,检验节点和变量节点的量化步长分别乘以和除以预先选定的一个参数。仿真和现场可编程门阵列实现结果表明,与未量化的标准积译码算法相比,该算法的性能损失在0.1 dB以内;与同等性能的算法相比,该算法可以降低50%的硬件规模。

Efficient quantization algorithm for low-density parity-check code decoding

A variable step uniform quantization(VSUQ) sum-product algorithm(SPA) was developed to reduce the hardware complexity of low-density parity-check(LDPC) code decoding.The extrinsic information in the check nodes and bit nodes is quantized in the same quantization step.Then,the quantization steps for the check nodes and bit nodes are multiplied and divided by a predetermined parameter.Simulation and implementation using a field programmable gate array(FPGA) show that the performance degradation in the algorithm is within 0.1 dB comparing to the unquantized standard SPA,while reducing the hardware size by 50% comparing to a uniform quantization SPA with the same performance.