100MHz数字频率计的设计

100MHz数字频率计用VHDL语言编程设计,主要由五个模块组成,分别是测频控制信号发生器、十进制计数器、32位锁存器、分频器、动态扫描译码驱动器模块五部分构成。选用分频器将工作时钟分频后,用测频器测频,将被测频率信号经脉冲整形电路后作为计数器的计数脉冲,加入计数器的输入端,测量一定闸门时间内被测信号的脉冲个数,并将其计数值锁存进锁存器中,最后通过动态扫描译码器读出数值,该频率计精度高,可用于频率测量、机械转速测量等领域。

100MHz Digital Frequency Meter

100 MHz digital frequency meter with the VHDL language programming design,mainly is composed by five modules,measure the frequency pilot signal generator,decimal system counter,32-bit latch,frequency divider,Dynamic scanning decoding driver.Select and use frequency division implement after with the clock frequency division working,the implement measures frequency with measuring frequency,will the frequency signal counting pulse by that the pulse reshaping circuit queen is a counter be measured,add the counter input end,measure the pulse number the signal is measured within certain sluice gate time,read numerical value out finally and in the whose meter numerical value lock being stored receiving the lock exist implement,by the fact that development scans a decoder,fields such as owing a frequency meter accuracy height,but being used for frequency measurement,machinery rotation rate measurement.