| 电子时钟仿真及其FPGA实现 |
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| 引用本文： | 宋翠翠,董永鑫,郭华帅,陈同洲. 电子时钟仿真及其FPGA实现[J]. 中国传媒大学学报, 2009, 16(1) |
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| 作者姓名： | 宋翠翠 董永鑫 郭华帅 陈同洲 |
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| 作者单位： | 中国传媒大学信息工程学院,北京,100024 |
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| 摘 要： | 基于VHDL语言设计各个模块,用原理图文件的方式将各个模块连接起来,通过调试仿真,最终实现了24小时时钟的正常显示,清零,暂停,调整时间的功能,并将其烧录至FLEX系列EPF 10k10LC84-4此种型号的芯片中,按照设计的管脚设置对电路板进行连线,测试并验证了各项功能的正确性.
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| 关 键 词： | 编译 仿真 |
Simulation and FPGA Implementation on Electronic Clock |
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| SONG Cui-cui,DONG YONG-xin,GUO Hua-shuai,CHEN Tong-zhou. Simulation and FPGA Implementation on Electronic Clock[J]. Journal of Communication University of China Science and TEchnology, 2009, 16(1) |
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| Authors: | SONG Cui-cui DONG YONG-xin GUO Hua-shuai CHEN Tong-zhou |
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| Affiliation: | Information Engineering Institute;Communication University of China;Beijing 100024;China |
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| Abstract: | Our project is designed in VHDL.The modules are cooperative by the way of schematic diagram files,which can run as a 24-hour clock,including functions of the time displaying,clear,pause,etc.after the simulation and debug.Then we burn the programm into the EPF 10k10LC84-4,FLEX series,and verify the functions after the completation of the pins'connective on the circuit board according to the presetting. |
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| Keywords: | VHDL PLD |
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