高k栅栈MOSFET共振隧穿模型

针对高介电常数（k）栅堆栈金属氧化物场效应晶体管（Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET）实际结构,建立了入射电子与界面缺陷共振高k栅栈结构共振隧穿模型.通过薛定谔方程和泊松方程求SiO2和高k界面束缚态波函数,利用横向共振法到共振本征态,采用量子力转移矩阵法求共振隧穿系数,模拟到栅隧穿电流密度与文献中实验结果一致.讨论了高k栅几种介质材料和栅电极材料及其界面层（IL）厚度、高k层（HK）厚度对共振隧穿系数影响.结果表明,随着HfO2和Al2O3厚度减小,栅栈结构共振隧穿系数减小,共振峰减少.随着La2O3厚度减小,共振峰减少,共振隧穿系数却增大.随着SiO2厚度增大,HfO2,Al2O3和La2O3基栅栈结构共振隧穿系数都减小,共振峰都减少.TiN栅电极HfO2,Al2O3和La2O3基栅栈比相应多晶硅栅电极栅栈结构共振隧穿系数小很多,共振峰少.     

Strong polarization enhancement in asymmetric three-component ferroelectric superlattices

Theoretical predictions--motivated by recent advances in epitaxial engineering--indicate a wealth of complex behaviour arising in superlattices of perovskite-type metal oxides. These include the enhancement of polarization by strain and the possibility of asymmetric properties in three-component superlattices. Here we fabricate superlattices consisting of barium titanate (BaTiO3), strontium titanate (SrTiO3) and calcium titanate (CaTiO3) with atomic-scale control by high-pressure pulsed laser deposition on conducting, atomically flat strontium ruthenate (SrRuO3) layers. The strain in BaTiO3 layers is fully maintained as long as the BaTiO3 thickness does not exceed the combined thicknesses of the CaTiO3 and SrTiO3 layers. By preserving full strain and combining heterointerfacial couplings, we find an overall 50% enhancement of the superlattice global polarization with respect to similarly grown pure BaTiO3, despite the fact that half the layers in the superlattice are nominally non-ferroelectric. We further show that even superlattices containing only single-unit-cell layers of BaTiO3 in a paraelectric matrix remain ferroelectric. Our data reveal that the specific interface structure and local asymmetries play an unexpected role in the polarization enhancement.     

新一代CMOS器件栅介质材料研究进展

随着微电子技术的飞速发展,按照摩尔定律发展的要求,SiO2的极限厚度已经成为Si基集成电路提高集成度的瓶颈。寻求代替SiO2的其它新一代高k栅介质已成为当今微电子技术发展的必然趋势。文章介绍了几种最有可能成为下一代栅介质的高k材料,并对其研究进展和存在的问题进行了阐述。     

A high-mobility electron gas at the LaAlO3/SrTiO3 heterointerface

Polarity discontinuities at the interfaces between different crystalline materials (heterointerfaces) can lead to nontrivial local atomic and electronic structure, owing to the presence of dangling bonds and incomplete atomic coordinations. These discontinuities often arise in naturally layered oxide structures, such as the superconducting copper oxides and ferroelectric titanates, as well as in artificial thin film oxide heterostructures such as manganite tunnel junctions. If polarity discontinuities can be atomically controlled, unusual charge states that are inaccessible in bulk materials could be realized. Here we have examined a model interface between two insulating perovskite oxides--LaAlO3 and SrTiO3--in which we control the termination layer at the interface on an atomic scale. In the simple ionic limit, this interface presents an extra half electron or hole per two-dimensional unit cell, depending on the structure of the interface. The hole-doped interface is found to be insulating, whereas the electron-doped interface is conducting, with extremely high carrier mobility exceeding 10,000 cm2 V(-1) s(-1). At low temperature, dramatic magnetoresistance oscillations periodic with the inverse magnetic field are observed, indicating quantum transport. These results present a broad opportunity to tailor low-dimensional charge states by atomically engineered oxide heteroepitaxy.     

Low-voltage organic transistors with an amorphous molecular gate dielectric

Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.     

作为高介电常数栅介质材料的LaErO_3薄膜热稳定性和电学性质的研究

采用脉冲激光淀积法在硅衬底上生长了LaErO3薄膜,用X射线衍射仪、X射线电子能谱仪、高分辨透射电子显微镜研究了该薄膜的热学和电学性质.通过电容-电压测量得到了较好的电容-电压曲线,计算得出等效SiO2厚度为1.4nm.通过高分辨电镜可以看出即使经过700℃30sN2中快速热退火处理LaErO3薄膜与硅衬底之间的反应层也仅有几个原子层的厚度.X射线电子能谱分析得到非常少量的SiO2在沉积的过程中形成.测量的热学和电学性质表明LaErO3薄膜是高介电常数栅介质材料非常有前途的候选材料.     

Artificial charge-modulationin atomic-scale perovskite titanate superlattices

The nature and length scales of charge screening in complex oxides are fundamental to a wide range of systems, spanning ceramic voltage-dependent resistors (varistors), oxide tunnel junctions and charge ordering in mixed-valence compounds. There are wide variations in the degree of charge disproportionation, length scale, and orientation in the mixed-valence compounds: these have been the subject of intense theoretical study, but little is known about the microscopic electronic structure. Here we have fabricated an idealized structure to examine these issues by growing atomically abrupt layers of LaTi(3+)O(3) embedded in SrTi(4+)O(3). Using an atomic-scale electron beam, we have observed the spatial distribution of the extra electron on the titanium sites. This distribution results in metallic conductivity, even though the superlattice structure is based on two insulators. Despite the chemical abruptness of the interfaces, we find that a minimum thickness of five LaTiO(3) layers is required for the centre titanium site to recover bulk-like electronic properties. This represents a framework within which the short-length-scale electronic response can be probed and incorporated in thin-film oxide heterostructures.     

基于转移矩阵法确定高k介质中泄漏电流共振隧穿机制的存在性

栅隧穿电流已成为制约MOS器件继续缩小的因素之一.为了掌握和控制高k栅栈的栅电流,必须全面了解其中存在的各种隧穿机制.考虑高k介质和二氧化硅间的界面陷阱,建立了高栅栈MOSFET中沟道与栅极交换载流子的双势垒隧穿物理模型.采用量子力学的转移矩阵方法,计算沟道电子通过高栅栈结构的透射系数,模拟得到的透射系数曲线随电子能量变化呈现峰谷振荡的特征.将本文模拟结果与非平衡格林函数及WKB近似方法模拟结果对比,通过论证得出电子能量低于高导带底的透射系数峰为共振隧穿机制所产生,而能量高于高k介质导带底的电子透射系数峰为直接隧穿的结论.     

Two-dimensional electron gas with universal subbands at the surface of SrTiO(3)

As silicon is the basis of conventional electronics, so strontium titanate (SrTiO(3)) is the foundation of the emerging field of oxide electronics. SrTiO(3) is the preferred template for the creation of exotic, two-dimensional (2D) phases of electron matter at oxide interfaces that have metal-insulator transitions, superconductivity or large negative magnetoresistance. However, the physical nature of the electronic structure underlying these 2D electron gases (2DEGs), which is crucial to understanding their remarkable properties, remains elusive. Here we show, using angle-resolved photoemission spectroscopy, that there is a highly metallic universal 2DEG at the vacuum-cleaved surface of SrTiO(3) (including the non-doped insulating material) independently of bulk carrier densities over more than seven decades. This 2DEG is confined within a region of about five unit cells and has a sheet carrier density of ～0.33 electrons per square lattice parameter. The electronic structure consists of multiple subbands of heavy and light electrons. The similarity of this 2DEG to those reported in SrTiO(3)-based heterostructures and field-effect transistors suggests that different forms of electron confinement at the surface of SrTiO(3) lead to essentially the same 2DEG. Our discovery provides a model system for the study of the electronic structure of 2DEGs in SrTiO(3)-based devices and a novel means of generating 2DEGs at the surfaces of transition-metal oxides.     

钛酸锶钡拉曼光谱的理论计算与实验研究

钛酸钡是一种重要的铁电体，在居里温度130 ℃附近介电常数最大，为了降低钛酸钡的居里温度，通常在钛酸钡中掺杂锶.采用水热合成法制备了钛酸锶钡粉末，并且建立2×2×1的超晶胞进行第一性原理计算.随着锶掺杂量的增加，其XRD衍射峰向右偏移，说明钛酸锶钡的晶胞结构逐渐从四方相转变到立方相.计算结果表明:随着锶掺杂量增加，钛酸锶钡的晶胞参数逐渐减小；晶胞参数c与a的比值逐渐减小，与实验相符；Raman光谱特征峰的强度逐渐减弱，说明掺杂后钛酸锶钡的自发极化程度逐渐减弱，Ti和O分别偏离晶胞体心和面心的位移逐渐减小.由于掺杂后钡原子被比其原子半径小的锶原子取代，使得晶胞参数变小，阻碍了Ti的自发偏移，Ti只需要较低的热振动能即可克服与O的库仑作用，稳定位于晶胞体心，居里温度(居里点)随之下降.     

Characterization of ultrathin SiO 2/Si interface grown by low temperature plasma oxidation

Ultrathin SiO 2 layers on Si (100) wafers were prepared by plasma oxidation at a low temperature (250℃). The analyses of X-ray photoelectron spectroscopy (XPS) and TEM reveal that the chemical composition of the oxide layer is stoichiometric SiO 2 and the SiO 2/Si interface is abrupt. The thickness of the ultrathin oxide layer obtained from XPS, capacitance-voltage (C-V) and ellipsometry measurements indicate a nonlinear time dependence. The high frequency C-V characterization of MOS structure shows that the fixed charge density in SiO 2 film is about 10 11 cm -2 . It is also shown that the strength of breakdown electrical field of SiO 2 film with 6 nm thickness is of the order of 10 6 Vcm -1 . These properties of the ultrathin SiO 2 layer ensure its application in silicon quantum devices.     

Electronic transport in nanometre-scale silicon-on-insulator membranes

The widely used 'silicon-on-insulator' (SOI) system consists of a layer of single-crystalline silicon supported on a silicon dioxide substrate. When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise, distinct from those of bulk silicon. The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used. Here we show--using scanning tunnelling microscopy, electronic transport measurements, and theory--that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the 'bulk' band structure of the thin silicon template layer. This interaction enables high-mobility carrier conduction in nanometre-scale SOI; conduction in even the thinnest membranes or layers of Si(001) is therefore possible, independent of any considerations of bulk doping, provided that the proper surface or interface states are available to enable the thermal excitation of 'bulk' carriers in the silicon layer.     

A III-V nanowire channel on silicon for high-performance vertical transistors

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.     

Preparation and characterization of barium strontium titanate/silicon nanoporous pillar array composite thin films by a sol-gel method

Barium strontium titanate (Ba_0.5Sr_0.5TiO₃, BST)/silicon nanoporous pillar array (Si-NPA) thin films were prepared by a spin-coating/annealing technique based on Si-NPA with micro/nano-structure. Both the isomer conversion of acetylacetone and the network structure combined by enol and Ti-alkoxide facilitate the formation of the BST sol and the subsequent crystallization. Before the perovskite BST begins to form, the intermediate phase (Ba,Sr)Ti₂O₅CO₃ is found. The boundary between BST and Si-NPA is of clarity and little interface diffusion, disclosing that Si-NPA is an ideal template substrate in the preparation of multifunctional composite films.     

Atomic-scale imaging of nanoengineered oxygen vacancy profiles in SrTiO3

At the heart of modern oxide chemistry lies the recognition that beneficial (as well as deleterious) materials properties can be obtained by deliberate deviations of oxygen atom occupancy from the ideal stoichiometry. Conversely, the capability to control and confine oxygen vacancies will be important to realize the full potential of perovskite ferroelectric materials, varistors and field-effect devices. In transition metal oxides, oxygen vacancies are generally electron donors, and in strontium titanate (SrTiO3) thin films, oxygen vacancies (unlike impurity dopants) are particularly important because they tend to retain high carrier mobilities, even at high carrier densities. Here we report the successful fabrication, using a pulsed laser deposition technique, of SrTiO3 superlattice films with oxygen doping profiles that exhibit subnanometre abruptness. We profile the vacancy concentrations on an atomic scale using annular-dark-field electron microscopy and core-level spectroscopy, and demonstrate absolute detection sensitivities of one to four oxygen vacancies. Our findings open a pathway to the microscopic study of individual vacancies and their clustering, not only in oxides, but in crystalline materials more generally.     

基于钛酸锶钡陶瓷的宽带频率选择表面设计

设计了一种基于钛酸锶钡陶瓷的新型宽带频率选择表面,其基本单元尺度为亚波长,按照三角晶格进行排列。通过调节单元的共振频率,实现了三个共振模式耦合而形成宽带工作的阻带。模拟结果表明,电磁波在0°入射的时候,频率选择表面的带宽为7.8 GHz。当钛酸锶钡陶瓷的相对介电常数由115降低到85时,阻带带宽可以增大到8.7 GHz。该设计具有良好的宽带特性,在电子对抗和隐身领域具有重要的军事价值。     

Au／MgO（001）界面上Au原子与点缺陷相互作用的第一性原理研究

采用基于密度泛函理论的第一性原理平面波赝势方法,系统地研究了Au／MgO（001）界面中8种晶格匹配方式的电子结构和化学键特征．界面处原子间距、界面能以及电子密度分布显示不同点缺陷与Au原子层相互作用的微观机制存在明显差异,并且界面体系稳定性和Au原子生长模式与界面原子排列方式密切相关．     

Electronic reconstruction at an interface between a Mott insulator and a band insulator

Surface science is an important and well-established branch of materials science involving the study of changes in material properties near a surface or interface. A fundamental issue has been atomic reconstruction: how the surface lattice symmetry differs from the bulk. 'Correlated-electron compounds' are materials in which strong electron-electron and electron-lattice interactions produce new electronic phases, including interaction-induced (Mott) insulators, many forms of spin, charge and orbital ordering, and (presumably) high-transition-temperature superconductivity. Here we propose that the fundamental issue for the new field of correlated-electron surface/interface science is 'electronic reconstruction': how does the surface/interface electronic phase differ from that in the bulk? As a step towards a general understanding of such phenomena, we present a theoretical study of an interface between a strongly correlated Mott insulator and a band insulator. We find dramatic interface-induced electronic reconstructions: in wide parameter ranges, the near-interface region is metallic and ferromagnetic, whereas the bulk phase on either side is insulating and antiferromagnetic. Extending the analysis to a wider range of interfaces and surfaces is a fundamental scientific challenge and may lead to new applications for correlated electron materials.     

选择性湿法刻蚀制备内嵌碳纳米管的沟槽结构

提出一种“自下而上”的纳米结构的制备方法。在生长有碳纳米管的氧化硅表面沉积数纳米的钯金属膜后, 用氢氟酸刻蚀, 得到完全由碳纳米管引导的沟槽结构, 并且碳纳米管沿沟槽分布在其底部。通过导电原子力显微镜对沟槽内的碳纳米管的表征, 发现其仍然具有良好的导电性。在碳纳米管和钯金属膜之间增加一层磁控溅射沉积的氧化硅, 可以增加沟槽的深宽比。通过降低钯金属膜的致密程度, 沟槽的开口宽度可降至100 nm左右。该方法制备的结构可以进一步用来构建基于碳纳米管的纳电子器件。     

高含钡锶离子采出水成垢趋势分析方法研究

油田注水开发导致采出液的含水量逐年增加,部分区块采出液水体结垢导致集输管线堵塞等各种问题日益严重。根据耿83区高含钡锶离子的特点,分别采用常规水分析方法、原子吸收光谱法和等离子体原子发射光谱法测试采出水和注入水的水样离子组成成分、水样矿化度、水型等。实验结果表明,在高矿化度含多种阳离子的水溶液中,原子吸收光谱法测试结果更准确。采用原子吸收光谱法对该区块结垢特征系统分析,计算结垢理论值,得出主要为硫酸钡和硫酸锶垢型。将现场垢样通过能谱和扫描电镜分析,验证得到与水样分析出的垢体一致。该方法能准确判定出垢体和垢型,为进一步采取有效的防垢、清垢措施提供重要的依据。