| 基于FPGA的二维双向CFAR处理器的设计与实现 |
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| 引用本文： | 高巍,谢芳,蒋荣堃,杨昊,王晓华,吕余青.基于FPGA的二维双向CFAR处理器的设计与实现[J].北京理工大学学报,2021,41(5):536-541. |
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| 作者姓名： | 高巍 谢芳 蒋荣堃 杨昊 王晓华 吕余青 |
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| 作者单位： | 北京理工大学信息与电子学院,北京 100081;中国船舶集团有限公司第八研究院,江苏,南京210000 |
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| 摘 要： | 在雷达自适应检测中，一维恒虚警率（CFAR）处理器只能在单一维度进行目标检测.因此基于一维CFAR算法提出一种在现场可编程门阵列（FPGA）上实现的二维双向CFAR处理器结构.该结构同时考虑了距离维和多普勒维的检测信息，提高了检测精确度.该处理器支持CA、GO、SO、OSCA、OSGO、OSSO等6种CFAR检测算法可选，支持参考单元数量、保护单元数量、排序值、门限因子可配置，可在多种杂波环境下应用.实验结果表明，当信噪比为12 dB时，6种检测算法检测概率均在80%以上；该处理器的最大综合时钟频率为137 MHz，使用的逻辑单元远小于FPGA资源，可以满足工程实际应用要求.
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| 关 键 词： | 雷达自适应检测 二维CFAR 现场可编程门阵列(FPGA) 可配置 |
| 收稿时间： | 2019/12/31 0:00:00 |
Design and Implementation of Two-Dimensional Bidirectional CFAR Processor Based on FPGA |
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| GAO Wei,XIE Fang,JIANG Rongkun,YANG Hao,WANG Xiaohua,L Yuqing.Design and Implementation of Two-Dimensional Bidirectional CFAR Processor Based on FPGA[J].Journal of Beijing Institute of Technology(Natural Science Edition),2021,41(5):536-541. |
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| Authors: | GAO Wei XIE Fang JIANG Rongkun YANG Hao WANG Xiaohua L Yuqing |
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| Affiliation: | 1. School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China;2. Eighth Research Institute of China Shipbuilding Corporation, Nanjing, Jiangsu 210000, China |
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| Abstract: | In radar adaptive detection, one-dimensional CFAR processor can only perform target detection in a single dimension.Based on the one-dimensional CFAR algorithm, a new method was proposed to implement a two-dimensional bidirectional CFAR processor structure on FPGA.Considering the detection information of the distance dimension and the Doppler dimension synchronously,the structure was arranged to improve the detection accuracy.The processor was designed for six algorithm options,supporting CA,GO,SO,OSCA,OSGO,and OSSO CFAR detectors,and also supporting configurable number of reference cells,number of protection cells,ranking values,and threshold factors to be applied in a variety of clutter environments.Experimental results show that,when the signal-to-noise ratio is 12 dB,the detection probability of the six detectors can reach above 80%.The maximum integrated clock frequency of this processor is 137 MHz,and the logic unit used is much smaller than the FPGA resources,which can meet the requirements of practical engineering applications. |
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| Keywords: | radar adaptive detection two-dimensional CFAR field programmable gate array(FPGA) configurable |
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