| 基于训练方式的存储器时钟信号的自适应同步 |
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| 引用本文： | 陆辰鸿,胡越黎,周俊.基于训练方式的存储器时钟信号的自适应同步[J].上海大学学报(自然科学版),2015,21(4):393-401. |
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| 作者姓名： | 陆辰鸿 胡越黎 周俊 |
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| 作者单位： | (1. 上海大学新型显示技术及应用集成教育部重点实验室, 上海200072; 2. 上海大学机电工程与自动化学院, 上海200072) |
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| 基金项目： | 国家自然科学基金资助项目(61376028); 上海市科委基金资助项目(13111104600) |
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| 摘 要： | 存储器是现代电子系统的核心器件之一, 常用于满足不同层次的数据交换与存储需求. 然而频率提高、时钟抖动、相位漂移以及不合理的布局布线等因素, 都可能导致CPU对存储器访问稳定性的下降. 针对同步动态随机读写存储器(synchronous dynamic random access memory, SDRAM)接口的时钟信号提出了一种自适应同步的训练方法, 即利用可控延迟链使时钟相位按照训练模式偏移到最优相位, 从而保证了存储器访问的稳定性. 在芯片内部硬件上提供了一个可通过CPU控制的延迟电路, 用来调整SDRAM时钟信号的相位. 在系统软件上设计了训练程序, 并通过与延迟电路的配合来达到自适应同步的目的：当CPU访问存储器连续多次发生错误时, 系统抛出异常并自动进入训练模式. 该模式令CPU在SDRAM中写入测试数据并读回, 比对二者是否一致. 根据测试数据比对结果, 按训练模式调整延迟电路的延迟时间. 经过若干次迭代, 得到能正确访问存储器的延迟时间范围, 即“有效数据采样窗口”,取其中值即为SDRAM最优时钟相位偏移. 完成训练后对系统复位, 并采用新的时钟相位去访问存储器, 从而保证读写的稳定性. 仿真实验结果表明, 本方法能迅速而准确地捕捉到有效数据采样窗口的两个端点位置, 并以此计算出最佳的延迟单元数量, 从而实现提高访问外部SDRAM存储器稳定性的目的.
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| 关 键 词： | 同步动态随机读写存储器 训练 延迟电路 自适应 |
| 收稿时间： | 2013-11-27 |
Self-adaptive synchronization of memory interface based on training |
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| LU Chen-hong,HU Yue-li,ZHOU Jun.Self-adaptive synchronization of memory interface based on training[J].Journal of Shanghai University(Natural Science),2015,21(4):393-401. |
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| Authors: | LU Chen-hong HU Yue-li ZHOU Jun |
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| Affiliation: | (1. Key Laboratory of Advanced Display and System Applications, Shanghai University, Shanghai 200072, China; 2. School of Mechatronic Engineering and Automation, Shanghai University, Shanghai 200072, China) |
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| Abstract: | Memory is a core device in system on a chip (SoC) and other electronic systems for data exchange and storage at different levels. However, memory access errors may occur due to factors such as raise of frequency, jitter, phase drift, unreasonable placement and routing. An adaptive synchronize method focusing on the training of clock signal is designed for synchronous dynamic random access memory (SDRAM) interface to enhance stability of memory access. A CPU-controlled delay circuit is used to shift the phase of SDRAM clock signal. A training program is designed to cooperate with the delay module hardware for memory interface tuning. In the training mode, CPU writes test data to the memory and reads them back, judging whether they are matching or not. Training program tunes the delay circuit according to the test results. A valid data sampling window is obtained rapidly and accurately after several iterations. Using the method, the middle of the window is calculated, which is the optimal phase drift for SDRAM clock signal and can improve stability of memory access. |
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| Keywords: | adaptive delay circuit synchronous dynamic random access memory (SDRAM) training |
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