This paper design a 32 bit float multiplier. 2-steps booth algorithm be used and adopt Iterative array and Wallace-tree structure which are composed of inverse polarity CSA adders to create partial product. At last we give the result of design and verification.
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张菁. 32位并行浮点乘法器设计[J]. 科学技术与工程, 2009, 9(21): . zhang jing. Design of Floating-point 32 bit Parallel Multiplier[J]. Science Technology and Engineering,2009,9(21).
