As known that it’s very important to generate the big prime number during hardware design of RSA Encryption algorithms. A deterministic algorithm for hardware implementation of big prime number generation automatically is put forward, which is based on conventional screening methods by analyzing a variety of prime numbers. With this method, it can quickly and automatically generate prime numbers in the memory. The state machine framework is adopted for hardware implementation of the algorithm with VerilogHDL description language. The functional verification is one with Modelsim Simulation and the results show that it can automatically generate a prime number sequence quickly and accurately with this method, it provides a rich library of primes for RSA algorithm application.