In view of the structure characteristics of storage of low density parity check codes（LDPC）which are used in the second generation satellite digital video broadcasting standard（DVB-S2）, the encoding was finished using the improved codeword construction method, and then the check matrix was deduced using the similar method, the data overflow problem in the simulation process was overcome. Through comparing different decoding algorithms of LDPC, the reduced complexity Minimum-Sum decoding algorithm was used and the performance of different code rates of LDPC was simulated in software. From the hardware implementation of decoder point of view, fixed-point representation instead of floating-point was proposed, and the effect of the number of iterations and the quantization on the input data and inner variables of decoder on the performance was investigated. Simulation analysis showed that this study reduced the complexity of the decoder hardware implementation with small performance penalty in storage and run time and so on, hence leading to lower delay and power consumption in the whole radio receiver. It provides a theoretical basis for hardware implementation.